An integrated circuit (IC) is manufactured using a multi-phase process involving photographic and chemical process steps. In general, common phases in fabricating an IC can include, but are not limited to, front-end-of-line (FEOL) processing, back-end-of-line (BEOL) processing, wafer testing, die preparation, and packaging. FEOL processing generally refers to the formation of circuit elements such as transistors. BEOL processing generally refers to the formation of metal layers and interconnects. Wafer testing or wafer sort generally refers to functional testing that can be performed on dies while still in wafer form. Die preparation generally refers to preparatory steps applied to dies for packaging. Finally, packaging generally refers to the process of mounting or placing dies within plastic, ceramic, or other packages that facilitates use of the IC within another system, e.g., upon a circuit board.
Typically, ICs are characterized in terms of performance. Performance often is measured in terms whether the IC is able to perform within established design requirements relating, for example, to operating frequency, signal fidelity, signal response, or the like. Each IC can be classified into one of a plurality of different “bins,” where each bin refers to a particular range of performance typically within the design requirements. Each IC can be priced and sold according to the particular bin to which the IC is classified. Performance analysis also facilitates the identification of ICs that do not meet minimum design requirements.
In general, due to the high operating frequencies of many modern ICs, performance testing is not performed until the dies are no longer in wafer form and have been packaged. Though wafer testing does test various functional aspects of a die, wafer testing at frequencies higher than approximately 50 megahertz or so, e.g., into the gigahertz range, is not feasible. High speed testing during wafer testing, or sort, is infeasible in large part due to the probe card technology that is used and the physical form of the dies in wafer form. For example, the probe tips of the probe card contact probe pads on the bare wafer. The signal path between the probe tips and the measurement equipment is not a controlled impedance signal path. Further, there can be significant distance between the measurement equipment and the source of the signal being measured from the wafer. These factors, among others, e.g., parasitic capacitances and the like, can significantly inhibit testing at full operational speeds of the dies while in wafer form.